A flash memory is a non-volatile memory, which can maintain the information stored thereon even when no power is supplied thereto. This means an electronic device using the flash memory does not need to waste electric power for memorizing data. The flash memory is also rewritable, small in volume with high memory capacity, and easy to carry. Therefore, flash memories are particularly suitable for use with portable devices. Currently, NOR flash memories have been used not only on motherboards of computers for storing BIOS (basic input/output system) data, but also on mobile phones and hand-held devices for storing system data. In addition, the flash memory offers fast read access speed to satisfy the demands for quick boot speed of hand-held devices.
With the progress in different technical fields, the process technique for flash memory also moves into the era of nanometer technology. For the purpose of increasing the device operating speed, increasing the device integration, and reducing the device operating voltage, it has become a necessary trend to reduce the gate channel length and the oxide layer thickness of the device. The reduction of device dimensions increases not only the density of integrated circuit (IC) per unit area, but also the current driving ability of the device. However, there are also problems caused by such reduction of device dimensions. For example, the gate linewidth of the device has been reduced from the past micron scale (10−6 meter) to the current nano scale (10−9 meter), and the short channel effect (SCE) becomes more serious with the reduction of device dimensions and gate linewidth. One of the solutions to avoid influences of short channel effect on the device is to reduce the source/drain junction depth.
For instance, the lightly-doped drain (LDD) enables the device to have an increased breakdown voltage, improved critical voltage property, and reduced hot carrier effect. While the LDD reduces the high electric field at the drain junction and effectively upgrades the reliability of the device, the LDD with shallow junction depth tends to be punched through in the etching process for forming contact hole to thereby damage the memory structure. To avoid damage of memory structure due to punch-through of the LDD, a highly-doped ion implantation process would usually be performed to implant a highly-doped drain (HDD) region to overlap with the LDD region. As a result, the flash memory structure can have a reduced drain junction depth to improve the short channel effect while the lightly-doped drain region is protected from being punched through during an etching process for forming contact hole.
However, as can be seen from FIG. 10, which is a sectional view of a conventional flash memory structure, when the above-described highly-doped ion implantation process is performed to form an HDD region 134 to overlap with an LDD region 132 between two gate structures 130, a junction 136 between the HDD region 134 and the LDD region 132 would have a relatively weak electric connection. When the LDD region is further reduced in the junction depth to avoid the short channel effect, the electric connection between the HDD region 134 and the LDD region 132 will become weaker to adversely affect the carrier mobility in the flash memory.
Therefore, it is very important to solve the problem of weak electric connection at the junction between the HDD region and the LDD region while the problems of short channel effect and punch-through of LDD region are avoided, so that the carrier mobility in the memory would not become lowered.